A semiconductor device chip often has two types and/or sizes of complementary metal-oxide semiconductor (CMOS) transistors on a single chip. One type is typically adapted for operation at a low supply voltage and another type typically adapted for operation at a higher supply voltage.
The low supply voltage transistors, referred to herein as the logic or core transistors, are used internal to the chip. Logic transistors are usually in the central part of the chip and are optimized for high packing density and performance. Logic transistors are smaller and have a thin gate oxide layer to maximize speed at low voltages.
The high supply voltage transistors are usually used to communicate to external devices/chips and are hence referred to as I/O (input/output) transistors. These transistors are larger, and have a thicker gate oxide layer for reliable high voltage operation. The use of two different supply voltages requires two different gate oxide thicknesses. For example, I/O transistors can often have a gate oxide thickness 2 to 4 times thicker than logic transistors.
Variations between implants received by the logic transistors and the I/O transistors require the use of two separate sets of masks. Optimizing both sets requires 4-5 additional masks. Tests using identical implants for both the low voltage and high voltage transistors, while preferable from a fabrication standpoint, do not provide high voltage transistors that meet the necessary lifetime and performance specifications. The high doping necessary for the logic transistors causes the periphery I/O transistors to have too high an electrical field, even though the oxide thickness is increased for these transistors. As a result, while the logic transistor threshold voltage (VT) is at the target value, the I/O transistor threshold voltage (VT) is too high and the I/O transistor's performance degrades.
FIGS. 2A-2D depict conventional methods for forming a semiconductor device having isolated regions of a logic NMOS transistor, a logic PMOS transistor, an I/O NMOS transistor, and an I/O PMOS transistor. In FIG. 2A, a blanket P-type substrate implant 40 is performed to set a threshold voltage (VT) of the I/O NMOS transistor. In FIG. 2B, the conventional 110 PMOS transistor, the logic PMOS transistor, and the I/O NMOS transistor are covered by a photo-resist 50, exposing only the logic NMOS region to form a DNWELL at 55 in the logic NMOS transistor.
In FIG. 2C, when standard NWELL pattern is performed (see 65) to form the logic PMOS transistor, the I/O PMOS transistor is also exposed to the NWELL implant by a photo-resist 60. In FIG. 2D, when the PWELL pattern is performed (see 75) in the conventional logic NMOS transistor by using a photo-resist 70, the I/O NMOS transistor is also exposed to the PWELL implant. This exposure of the I/O NMOS transistor can affect the threshold voltage of the I/O NMOS transistor that are previously set in FIG. 2A.
Thus, there is a need to overcome these and other problems of the prior art and to provide fabrication methods for CMOS devices with suitable I/O transistor threshold voltage (VT) but without using additional masks.